In order for high-speed wireless networks to operate effectively, it is important that the transmitting channel maintain a stable average power for its transmissions. This stable level of transmission is particularly important to the receiving channel of the network.
FIG. 1 is a schematic drawing of a typical physical layer architecture (PHY) for a transmitter. The particular circuit illustrated in FIG. 1 is the PHY for a Single-Input Single-Output (SISO) system using Orthogonal Frequency Division Multiplexing (OFDM), as used in various wireless Large Area Network (LAN) architectures, including the IEEE standard Multi-Mode 802.11 a/b/g (also known as Wifi) and High-Speed 802.11n architectures. This PHY transmission chain includes four main physical modules. The Medium Access Control (MAC) layer 102 is the link between the logical layers of the network and the physical layer. This module effectively requests a particular setting or value for the average output power level of the transmission. The digital signal processor (DSP) 110 is the module that generates the coded signal and converts it from a digital signal to an analogue radio frequency (RF) signal using two digital-to-analogue converters (DAC) 118. The radio frequency integrated circuit (RFIC) 120 mixes the quadrature and in-phase signals to provide the final signal to be transmitted. The forth module is the power amplifier (PA) module 130 that boosts the power level of the signal to the required output power level before it reaches the transmission antenna 144.
The average transmitted RF power level 142 is equal to the average input RF power level 132 supplied to the power amplifier (PA) 134 multiplied by the gain of the PA 134. The average input RF power level 132 is set at two points in the transmission chain. The transmission power control (TPC) fine register 146 in the MAC layer 102 controls the input to the DACs 118, providing control of the input RF power level 132 to 0.25 dB resolution. The transmission power control (TPC) coarse register 148 controls the radio frequency (RF) attenuator 126 on the RFIC 120 providing control of the average input RF power level 132 with 2 dB resolution.
Proper operation of the receiver unit of the wireless network requires a steady average transmitted RF power level 142. As seen from the discussion of the PHY layout above, the MAC layer 102, via its transmission power control registers, only has effective control of the average input RF power level 132. The transmission power control algorithm effectively assumes that the gain of the power amplifier (PA) module 130 is invariant with time. Temperature variations, however, cause the gain of the PA 134 to vary. To maintain a constant transmitted RF power level 142 it is necessary to add a feed back loop that compensates for temperature and keeps the gain of the PA 134 at a constant value. This is typically accomplished by having a diode detector 139 monitor the transmitted RF power level 142 and relay the result to a 7-bit auxiliary ADC 150 on the digital signal processor (DSP) 110. The DSP 110 runs an appropriate algorithm to monitor average output power and uses a 6-bit power DAC 119 to adjust the PA gain appropriately by setting the value of the PA bias current via the PA bias 138.
The details of such prior art power amplifier (PA) control circuits are discussed in detail in, for instance, U.S. Pat. No. 6,907,025 issued to Demir et al. on Jun. 14, 2005, which is hereby incorporated by reference.
Such methods of controlling the PA gain are well suited to situations where the gain may vary rapidly. In a typical LAN transmitter PHY, the variation in transmitted RF power level due to PA gain change with temperature happens relatively slowly. What is needed is a lower cost method to control the gain of a power amplifier to compensate for variations that are gradual with time.